As the technology for manufacuring integrated circuits progresses, it is becoming possible to put more and more discrete logic components on a single integrated circuit chip. For instance, there can be thousands of discrete logic components, such as, AND-gates, OR-gates, inverters and registers, on a single integrated circuit chip. However, due to limitations in packaging technology, the number of input and output ports to a given integrated circuit chip is limited. Thus, thousands of discrete logic components must be served typically by on the order of a few dozen input/output (I/O) ports. The small number of input/output ports available for a given integrated circuit thus severely restricts the flexibility in design of logic circuits implemented on integrated circuit chips.
Flexibility in design in particularly important for devices such as programmable array logic devices. In a programmable array logic device, a user of the device configures the logic array according to a specific need using field programming techniques. Since the user is constrained in his design choices by the configuration of the input/output pins, the utility of the programmable logic array is limited.
A prior U.S. patent application owned by the assignee in common with the present application, entitled APPARATUS FOR PRODUCING ANY ONE OF A PLURALITY OF SIGNALS AT A SINGLE OUTPUT, Ser. No. 433,253, filing date Oct. 7, 1982, addresses one way in which the configuration of input/output ports may be made more flexible. There, the user is able to select one of two types of output signals for a given output pin by setting a selector means using field programming techniques, such as blowing a fuse or not blowing the fuse, when the designer sets up the logic circuit on the chip. Thus, for example, the designer is able to locate registered outputs and combinatorial outputs on the I/O pins as he desires for a selected logic array package.
Another way in which to increase the flexibility of the design for programmable array logic devices of the prior art provides selectable feedback in the output logic so that the designer may choose using field programming techniques to provide a feedback path directly from the I/O pin to the logic array, in effect, treating the I/O pin as an input pin, or to select a registered output from the logic array as feedback. This sort of feedback system is described in product literature for the Advanced Micro Devices 24-pin IMOX.TM. Programmable Array Logic Device designated the AmPAL22V10 (PAL is a registered trademark of Monolithic Memories, Inc.). An advanced information sheet concerning the AMPAL22V10 was released by Advanced Micro Devices, Inc., Sunnyvale, Calif. dated June, 1983. This advanced information can be referred to for further background to the present invention.
Both the output selector and the feedback selector of the prior art mentioned above involved a designed-in or field programmed selection of the type of feedback or the type of output for a particular I/O pin. Accordingly, the user was limited to one configuration of each I/O pin for the device. Since it is desirable to provide a flexible output logic circuit, there is a need for an output logic circuit which provides for increased flexibility and overcomes the limitations of the prior art.
In addition, while the user could configure each I/O pin as an output logic circuit in the prior art, it is very often desirable to configure an I/O pin also as an input logic circuit. Furthermore, because of the use of such logic circuits in sequencers which employ internal state counters, it is often desirable to deploy a register within the logic circuit as an input, output or buried state register or alternatively as an input or output transparent latch. Accordingly, there is need for an input/output circuit which can be flexibly configured in either an input or an output mode and in which a register/latch can be flexibly utilized. A need for control of the feedback to the logic array, control over enabling of the output signal and flexibility in the manner of preloading, resetting and presetting of the register are recognized as desirable features missing from output logic circuits.
Furthermore, it is often desirable to allow clocking of the register/latch of individual output logic circuits from the logic array as well as from the usual clock, with selection by the user. It may even be desirable to permit user-selection from a pair of clocks, particularly when the integrated circuit chips employing the output logic circuits are deployed in two banks, each with its own clock.